Discussion:
Compiler Error
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Xiao Liang
2003-09-25 23:22:56 UTC
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Hi,

I was trying to complile mult_test.v, mult.v and ALU_struct.v, makefile
gives the following results:

Parsing design file 'mult_test.v'
Parsing design file 'mult.v'
Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with
+v2k
to support this construct
Comma separated sensitivity lists.
"mult.v", 50
Parsing design file 'ALU_struct.v'
1 error

What does that mean? Is there a way to get around it?

Thanks,
Xiao
Joel VanLaven
2003-09-25 23:41:48 UTC
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My guess is that you are using incorrect syntax in the:

always @(a or b or c) portion of your code.

like maybe you are doing:

always @(a,b,c)

Since none of the code I have ever used or ever seen has given this
error, I might be wrong. I'm simply basing my guess on the text of the
error.

-- Joel
Post by Xiao Liang
Hi,
I was trying to complile mult_test.v, mult.v and ALU_struct.v, makefile
Parsing design file 'mult_test.v'
Parsing design file 'mult.v'
Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with
+v2k
to support this construct
Comma separated sensitivity lists.
"mult.v", 50
Parsing design file 'ALU_struct.v'
1 error
What does that mean? Is there a way to get around it?
Thanks,
Xiao
Joel VanLaven
2003-09-26 00:18:34 UTC
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Oh yeah, also I think the error is on line 50 of mult.v and I have
verified that my guess will generate the same error.

-- Joel
Post by Xiao Liang
Hi,
I was trying to complile mult_test.v, mult.v and ALU_struct.v, makefile
Parsing design file 'mult_test.v'
Parsing design file 'mult.v'
Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with
+v2k
to support this construct
Comma separated sensitivity lists.
"mult.v", 50
Parsing design file 'ALU_struct.v'
1 error
What does that mean? Is there a way to get around it?
Thanks,
Xiao
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